| Title: |
Highly‐Effective Thermoelectric Cooling for Power Semiconductor Devices Packed with Thermal‐Expansion Offset and Flame Retardancy Epoxy Resin. |
| Authors: |
Li, You; Xiong, Tianshun; Ge, Lang; Liu, Dongjie; Ma, Wenyuan; Gang, Shuangfu; Li, Xin; Jiang, Qinghui; Luo, Yubo; Yang, Junyou |
| Source: |
Advanced Functional Materials; 9/18/2025, Vol. 35 Issue 38, p1-9, 9p |
| Subject Terms: |
POWER semiconductors; EPOXY resins; THERMAL expansion; STRAINS & stresses (Mechanics); THERMOELECTRIC cooling; FIREPROOFING; COMPOSITE materials; THERMAL conductivity |
| Abstract: |
The high‐power‐density and high‐temperature operation of third‐generation power semiconductor devices (e.g., SiC/GaN) is limited by epoxy resin (EP)‐based packaging materials due to three key challenges: (1) Low thermal conductivity brings heat accumulation; (2) High interfacial stress from the ≈ 20 times higher thermal expansion coefficient of EP versus SiC/GaN causes thermal cycling‐induced interfacecracks, significant performance or lifespan degradation and even device failure; (3) The flammable nature of EP enhances the risk factor caused by thermal runaway. Herein, a thermal‐expansion offset and flame retardant Zn1.5Cu0.5P2O7 (ZCPO) is design with a negative thermal expansion coefficient of ‐20 × 10−6/ °C, within temperature ranges of 20 ∼ 190 °C, which enables to achieve a ceramic‐like thermal expansion coefficient (4 × 10−6/ °C) and UL‐94 V‐0 rating flame retardancy in ZCPO/EP‐61 composite for the first time. The perfectly matched thermal expansion coefficient minimizes the interfacial stress between EP and chips or thermoelectric cooler, thus a simple thermoelectric cooling architecture is designed for power semiconductor device without thermal interface material 2 (TIM2), which enables to achieve a cooling temperature of 26.85 °C, 8 °C lower than that with TIM2 (18.89 °C). [ABSTRACT FROM AUTHOR] |
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| Database: |
Complementary Index |