A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
| Title: | A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers |
|---|---|
| Authors: | Muhammad A. Nummer |
| Contributors: | The Pennsylvania State University CiteSeerX Archives |
| Source: | https://ece.uwaterloo.ca/~cdr/pubs/nummer_masc.pdf. |
| Collection: | CiteSeerX |
| Subject Terms: | Acknowledgements |
| Description: | I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. |
| Document Type: | text |
| File Description: | application/pdf |
| Language: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.489.6104 |
| Availability: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.489.6104 |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Accession Number: | edsbas.1C2A0841 |
| Database: | BASE |