| Title: |
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits |
| Authors: |
Ferres, Bruno; Oulkaid, Oussama; Moy, Matthieu; Radanne, Gabriel; Henrio, Ludovic; Raymond, Pascal; Khosravian, Mehdi |
| Contributors: |
VERIMAG (VERIMAG - IMAG); Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP); Université Grenoble Alpes (UGA); Compilation et Analyse, Logiciel et Matériel (CASH); Laboratoire de l'Informatique du Parallélisme (LIP); École normale supérieure de Lyon (ENS de Lyon); Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL); Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure de Lyon (ENS de Lyon); Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Centre Inria de Lyon; Institut National de Recherche en Informatique et en Automatique (Inria); Aniah; Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS); Centre Inria de Lyon |
| Source: |
ISSN: 1084-4309 ; ACM Transactions on Design Automation of Electronic Systems ; https://hal.science/hal-05185119 ; ACM Transactions on Design Automation of Electronic Systems, 2025, ⟨10.1145/3748327⟩. |
| Publisher Information: |
CCSD; Association for Computing Machinery |
| Publication Year: |
2025 |
| Collection: |
HAL Lyon 1 (University Claude Bernard Lyon 1) |
| Subject Terms: |
Electrical Rule Checking; Integrated Circuits; Electro-Static Discharge; Electrical OverStress; Static Verification; [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] |
| Description: |
International audience ; Hardware verification is crucial to ensure the quality of Integrated Circuits, and prevent costly bugs down the manufacturing flow. Electrical Rule Checking (ERC) is a verification step used to assert that a circuit complies with some electrical rules, from the absence of short-circuits to dedicated constructor rules. In this survey, we provide a global overview of existing ERC techniques at transistor-level, where voltage values are explicit. We propose a new classification method to compare the existing approaches based on their semantic modeling of circuits. This survey precisely describes transistor-level ERC research challenges and existing solutions. We believe it will help structure this research domain by positioning existing approaches with respect to each other. Obviously, a survey should also facilitate technological transfer and this one should help CAD vendors identify the most relevant approaches to integrate in their tools. Finally, we highlight several promising directions to improve the existing solutions. |
| Document Type: |
article in journal/newspaper |
| Language: |
English |
| DOI: |
10.1145/3748327 |
| Availability: |
https://hal.science/hal-05185119; https://hal.science/hal-05185119v1/document; https://hal.science/hal-05185119v1/file/article.pdf; https://doi.org/10.1145/3748327 |
| Rights: |
https://creativecommons.org/licenses/by/4.0/ ; info:eu-repo/semantics/OpenAccess |
| Accession Number: |
edsbas.1CD877C0 |
| Database: |
BASE |