| Title: |
Enhancing Power-Performance-Area Scaling of Std-Cell, SRAM, and Analog Designs Through Design-Technology Co-Optimization |
| Authors: |
Deng, Jie; Sharma, Deepak; Yuan, Jun; Wang, Hao; Wang, Xiao-Yong; Lim, Bruce; Jung, Chulmin; Cheng, Jason; Gao, Yandong; Rasouli, Hadi; Kauffman, Anatoly; Chiang, Yuming; Denduluri, Raghava; Nallapati, Giri; Chidambaram, PR. Chidi |
| Source: |
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ; page 1-3 |
| Publisher Information: |
IEEE |
| Publication Year: |
2025 |
| Document Type: |
conference object |
| Language: |
unknown |
| DOI: |
10.23919/vlsitechnologyandcir65189.2025.11074818 |
| Availability: |
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074818; http://xplorestaging.ieee.org/ielx8/11074776/11074778/11074818.pdf?arnumber=11074818 |
| Rights: |
https://doi.org/10.15223/policy-029 ; https://doi.org/10.15223/policy-037 |
| Accession Number: |
edsbas.31CD610D |
| Database: |
BASE |