| Title: |
Interferences within a certifiable design methodology for high-performance multi-core platforms |
| Authors: |
Khelassi, Mohamed, Amine; Suchert, Felix; Amalou, Abderaouf; Lesage, Benjamin; Christmann, Anika; Hapka, Robin; Castrillon, Jeronimo; Asavoae, Mihail; Jan, Mathieu; Pagetti, Claire; Saidi, Selma |
| Contributors: |
Laboratoire Environnement de Conception & Architecture (LECA); Université Paris-Saclay-Département Systèmes et Circuits Intégrés Numériques (DSCIN (CEA, LIST)); Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)); Direction de Recherche Technologique (CEA) (DRT (CEA)); Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)); Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)); Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA); Technische Universität Dresden = Dresden University of Technology (TU Dresden); NANTES UNIVERSITÉ - École Centrale de Nantes (Nantes Univ - ECN); Nantes Université (Nantes Univ); Laboratoire des Sciences du Numérique de Nantes (LS2N); Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique); Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT)-NANTES UNIVERSITÉ - École Centrale de Nantes (Nantes Univ - ECN); Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ)-Nantes université - UFR des Sciences et des Techniques (Nantes univ - UFR ST); Nantes Université - pôle Sciences et technologie; Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ)-Nantes Université - pôle Sciences et technologie; DTIS, ONERA, Université de Toulouse Toulouse; ONERA-Communauté d'universités et établissements de Toulouse (Comue de Toulouse); Technische Universität Braunschweig = Technical University of Braunschweig Braunschweig; DFG, German Research Foundation Grant No. 505744711; ANR-22-CE92-0066,InterMCore,Interferences au sein d'une méthodologie de conception certifiable pour les plate-formes multi-coeurs haute performance(2022) |
| Source: |
Proceeding of ERTS 2026 on Embedded Real Time Systems ; 13th European Congress of Embedded Real Time Systems (ERTS) ; https://cea.hal.science/cea-05504739 ; 13th European Congress of Embedded Real Time Systems (ERTS), Feb 2026, Toulouse, France ; https://conference-erts.org/ |
| Publisher Information: |
CCSD |
| Publication Year: |
2026 |
| Collection: |
Université de Nantes: HAL-UNIV-NANTES |
| Subject Terms: |
Linux cgroups; Memory interferences; Machine learning; Memory interferences MLIR framework Machine learning Linux cgroups; MLIR framework; [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]; [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS] |
| Subject Geographic: |
Toulouse; France |
| Description: |
International audience ; The adoption of high-performance multi-core platforms in avionics and automotive systems introduces significant challenges in ensuring predictable execution, primarily due to shared resource interferences. Many existing approaches study interference from a single angle—for example, through hardware-level analysis or by monitoring software execution. However, no single abstraction level is sufficient on its own. Hardware behavior, program structure, and system configuration all interact, and a complete view is needed to understand where interferences come from and how to reduce them.In this paper, we present a methodology that brings together several tools that operate at different abstraction levels. At the lowest level, PHYLOG provides a formal model of the hardware and identifies possible interference channels using micro-architectural transactions. At the program level, machine learning analysis locates the exact parts of the code that are most sensitive to shared-resource contention. At the compilation level, MLIR-based transformations use this information to reshape memory access patterns and reduce pressure on shared resources. Finally, at the system level, Linux cgroups enforce static execution constraints to prevent highly interfering tasks from running together. The goal of our approach is to reduce memory interference and improve the system's predictability, thereby easing the certification process of multi-core systems in safety-critical domains. |
| Document Type: |
conference object |
| Language: |
English |
| Availability: |
https://cea.hal.science/cea-05504739; https://cea.hal.science/cea-05504739v1/document; https://cea.hal.science/cea-05504739v1/file/InterMCore.pdf |
| Rights: |
https://creativecommons.org/licenses/by/4.0/ ; info:eu-repo/semantics/OpenAccess |
| Accession Number: |
edsbas.563CF376 |
| Database: |
BASE |