| Title: |
Extension of ACETONE C code generator for multi-core architectures |
| Authors: |
Aït-Aïssa, Yanis; Carle, Thomas; Chichin, Sergei; Lesage, Benjamin; Pagetti, Claire |
| Contributors: |
AIRBUS Operations Ltd.; ONERA - The French Aerospace Lab Toulouse; ONERA; Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES); Institut de recherche en informatique de Toulouse (IRIT); Université Toulouse Capitole (UT Capitole); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Université Toulouse - Jean Jaurès (UT2J); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Université de Toulouse (EPE UT); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Toulouse Mind & Brain Institut (TMBI); Université Toulouse - Jean Jaurès (UT2J); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Université de Toulouse (EPE UT); Communauté d'universités et établissements de Toulouse (Comue de Toulouse)-Université Toulouse Capitole (UT Capitole); Communauté d'universités et établissements de Toulouse (Comue de Toulouse); DTIS, ONERA, Université de Toulouse Toulouse; ONERA-Communauté d'universités et établissements de Toulouse (Comue de Toulouse); ANR-23-IACL-0002,ANITI IA Cluster,Artificial and Natural Intelligence Toulouse Institute(2023) |
| Source: |
ERTS 2026 - Embedded Real Time Systems ; 13th European Congress of Embedded Real Time Systems (ERTS) ; https://hal.science/hal-05513962 ; 13th European Congress of Embedded Real Time Systems (ERTS), Feb 2026, Toulouse, France. ⟨10.82331/ERTS.2026.55⟩ ; https://conference-erts.org/ |
| Publisher Information: |
CCSD |
| Publication Year: |
2026 |
| Collection: |
Université Toulouse III - Paul Sabatier: HAL-UPS |
| Subject Terms: |
Graph Scheduling; Real-time safety-critical systems; Artificial Neural Networks implementation; [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE] |
| Subject Geographic: |
Toulouse; France |
| Description: |
International audience ; As the industry's interest in machine learning has grown in recent years, some solutions have emerged to safely embed them in safety-critical systems, such as the C code generator ACETONE. However, this framework is limited to generating sequential code, which cannot make most of the multi-core architectures.In this paper, we initiate an extension of ACETONE for the generation of parallel code by formally defining our processor assignment problem and surveying the state of the art on existing solutions. In the final paper, we will introduce the completed extension, including the implementation of the scheduling heuristic, the creation of templates implementing synchronization mechanisms, and an evaluation of the worst-case execution time of the framework's layers. |
| Document Type: |
conference object |
| Language: |
English |
| Relation: |
info:eu-repo/semantics/altIdentifier/arxiv/2603.08744; ARXIV: 2603.08744 |
| DOI: |
10.82331/ERTS.2026.55 |
| Availability: |
https://hal.science/hal-05513962; https://hal.science/hal-05513962v2/document; https://hal.science/hal-05513962v2/file/main.pdf; https://doi.org/10.82331/ERTS.2026.55 |
| Rights: |
https://creativecommons.org/licenses/by/4.0/ ; info:eu-repo/semantics/OpenAccess |
| Accession Number: |
edsbas.6263C05D |
| Database: |
BASE |