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Design and implementation of a low-voltage four selectable fractional-order differentiator in a 0.35 μm CMOS technology

Title: Design and implementation of a low-voltage four selectable fractional-order differentiator in a 0.35 μm CMOS technology
Authors: Abad, Alexander C.; Abulencia, Geoffrey L.; Yap, Roderick; Gonzalez, Emmanuel A.
Source: Faculty Research Work
Publisher Information: Animo Repository
Publication Year: 2018
Subject Terms: Dynamics; Microcontrollers; Metal oxide semiconductors; Complementary; Electrical and Electronics
Description: This study focused on the design and implementation of a four selectable Fractional-Order (0.2, 0.4, 0.6 and 0.8) Differentiator (FOD) in a 0.35 μm CMOS technology operated at 1.5 V supply. In comparison with previous research that use discrete components and generic microcontroller to switch an FOD from one order to the next, this design of a selectable FOD was realized in an analog microelectronics scale. The dimension of the Integrated Circuit (IC) layout was further reduced by employing reusability of capacitors and resistors. The whole chip layout of the design, excluding input/output pads has a dimension of 8.10×6.30 mm or equivalent to a final area of 51.03 mm2. The four possible orders of an FOD were characterized in terms of its magnitude and phase response in the working bandwidth from 10-1 kHz. Characterization was made using SPICE simulation tool and IC layout editor software. © Medwell Journals, 2018.
Document Type: text
Language: unknown
Relation: https://animorepository.dlsu.edu.ph/faculty_research/2603
DOI: 10.3923/jeasci.2018.1479.1486
Availability: https://animorepository.dlsu.edu.ph/faculty_research/2603; https://doi.org/10.3923/jeasci.2018.1479.1486
Accession Number: edsbas.62D4DF72
Database: BASE