| Title: |
Enhancing Keystone Security Against Cache Timing Attacks: A Modular Approach |
| Authors: |
Elmnaouri, Oussama; Cotret, Pascal; Lapotre, Vianney; Lagadec, Loïc |
| Contributors: |
Equipe Hardware ARchitectures and CAD tools (Lab-STICC_ARCAD); Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC); École Nationale d'Ingénieurs de Brest (ENIB); Université de Brest (UBO EPE)-Institut National Polytechnique de Bretagne (Bretagne INP)-Université de Brest (UBO EPE)-Institut National Polytechnique de Bretagne (Bretagne INP)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique); Institut Mines-Télécom Paris (IMT)-Institut Mines-Télécom Paris (IMT)-École Nationale Supérieure de Techniques Avancées (ENSTA); Institut Polytechnique de Paris (IP Paris)-Institut Polytechnique de Paris (IP Paris)-École Nationale d'Ingénieurs de Brest (ENIB); Institut Polytechnique de Paris (IP Paris)-Institut Polytechnique de Paris (IP Paris); École Nationale Supérieure de Techniques Avancées (ENSTA); Institut Polytechnique de Paris (IP Paris); Université de Bretagne Sud - Lorient (UBS Lorient); Université de Bretagne Sud (UBS); ANR-23-CE39-0011,SCAMA,Processeur sécurisé dès la conception contre les attaques microarchitecturales(2023) |
| Source: |
Colloque 2025 du GDR SoC2 ; https://hal.science/hal-05056900 ; Colloque 2025 du GDR SoC2, Jun 2025, Lorient, France. ; https://gdr-soc2-2025.sciencesconf.org/ |
| Publisher Information: |
CCSD |
| Publication Year: |
2025 |
| Collection: |
Université de Bretagne Occidentale: HAL |
| Subject Terms: |
Computer Architecture; Confidential Computing; Hardware Security; TEEs; SCAs; [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]; [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR]; [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE] |
| Subject Geographic: |
Lorient; France |
| Description: |
International audience ; Confidential computing includes various methods to enhance data security, notably by processing sensitive information within Trusted Execution Environments (TEEs). However, TEEs remain vulnerable to Side-Channel Attacks (SCAs), such as cache timing attacks, which exploit timing variations to extract confidential data. Existing TEE designs do not provide sufficient protection against these threats, highlighting the need for stronger security measures. This study focuses on integrating countermeasures specifically targeting timing and cache vulnerabilities within a TEE. The implementation will leverage the RISC-V architecture to explore its potential in mitigating SCA within TEE. |
| Document Type: |
conference object; still image |
| Language: |
English |
| Availability: |
https://hal.science/hal-05056900; https://hal.science/hal-05056900v1/document; https://hal.science/hal-05056900v1/file/GDR_SOC2.pdf |
| Rights: |
https://creativecommons.org/licenses/by/4.0/ ; info:eu-repo/semantics/OpenAccess |
| Accession Number: |
edsbas.6D9F67C6 |
| Database: |
BASE |