Scaling to the end of silicon with EDGE architectures
| Title: | Scaling to the end of silicon with EDGE architectures |
|---|---|
| Authors: | Doug Burger; Stephen W; Kathryn S; Mike Dahlin; Lizy K. John; Calvin Lin; Charles R; James Burrill; Robert G; Yoder |
| Contributors: | The Pennsylvania State University CiteSeerX Archives |
| Source: | http://www.cs.utexas.edu/users/dahlin/papers/edge-computer-2004.pdf. |
| Publication Year: | 2004 |
| Collection: | CiteSeerX |
| Description: | The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance. Instruction set architectures have long lifetimes because introducing a new ISA is tremendously disruptive to all aspects of a computer system. However, slowly evolving ISAs eventually become a poor match to the rapidly changing underlying fabrication technology. When that gap eventually grows too large, the benefits gained by renormalizing the architecture to match the underlying technology make the pain of switching ISAs well worthwhile. Microprocessor designs are on the verge of a |
| Document Type: | text |
| File Description: | application/pdf |
| Language: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.5319 |
| Availability: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.5319; http://www.cs.utexas.edu/users/dahlin/papers/edge-computer-2004.pdf |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| Accession Number: | edsbas.99787B38 |
| Database: | BASE |