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Overview of Complementary GaAs Technology for HighSpeed VLSI Circuits

Title: Overview of Complementary GaAs Technology for HighSpeed VLSI Circuits
Authors: Richard B. Brown; Bruce Bernhardt; Mike Lamacchia; Jon Abrokwah; Phiroze N. Parakh; Todd D. Basso; Spencer M. Gold; Sean Stetson; Claude R. Gauthier; David Foster; Brian Crawforth; Timothy Mcquire; Karem Sakallah; Ronald J. Lomax; Trevor N. Mudge
Contributors: The Pennsylvania State University CiteSeerX Archives
Source: http://www.eecs.umich.edu/~tnm/papers/cgaas98.pdf.
Publication Year: 1997
Collection: CiteSeerX
Subject Terms: of the
Description: —A self-aligned complementary GaAs (CGaAsTM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9V have demonstrated power-delay products of 0.01μW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPCTM-architecture microprocessor. This paper touches on the major aspects of the project, process technology, circuit design, packaging, architecture, CAD tools and software, with an emphasis on application
Document Type: text
File Description: application/pdf
Language: English
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.2659; http://www.eecs.umich.edu/~tnm/papers/cgaas98.pdf
Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.2659; http://www.eecs.umich.edu/~tnm/papers/cgaas98.pdf
Rights: Metadata may be used without restrictions as long as the oai identifier remains attached to it.
Accession Number: edsbas.AAB8BF19
Database: BASE