| Title: |
Modular SystemVerilog-UVM verification framework for the IGNITE pixel readout chip |
| Authors: |
Bermudez Marquez, C.F.; Beccherle, R.; Cadeddu, S.; Cossu, G.M.; Lai, A.; Loddo, F.; Pacher, L.; Piccolo, L. |
| Source: |
Journal of Instrumentation ; volume 21, issue 01, page C01026 ; ISSN 1748-0221 |
| Publisher Information: |
IOP Publishing |
| Publication Year: |
2026 |
| Description: |
Next-generation pixel-based read-out ASICs for high-energy physics experiments face demanding performance and integration requirements. A flexible, pixel-level simulation framework is essential to design, validate, and optimize the readout architecture and its building blocks. This contribution presents a SystemVerilog-UVM verification framework developed for the IGNITE project, a 28 nm CMOS pixel readout and processing ASIC designed for high-intensity 4D-tracking with spatial resolution |
| Document Type: |
article in journal/newspaper |
| Language: |
unknown |
| DOI: |
10.1088/1748-0221/21/01/c01026 |
| DOI: |
10.1088/1748-0221/21/01/C01026 |
| DOI: |
10.1088/1748-0221/21/01/C01026/pdf |
| Availability: |
https://doi.org/10.1088/1748-0221/21/01/c01026; https://iopscience.iop.org/article/10.1088/1748-0221/21/01/C01026; https://iopscience.iop.org/article/10.1088/1748-0221/21/01/C01026/pdf |
| Rights: |
http://creativecommons.org/licenses/by/4.0/ ; https://iopscience.iop.org/info/page/text-and-data-mining |
| Accession Number: |
edsbas.D3B9C393 |
| Database: |
BASE |