| Title: |
Gate Voltage Matching Investigation for Low-Power Analog Applications |
| Authors: |
Joly, Yohan; Lopez, Laurent; Truphemus, Laurent; Portal, Jean-Michel; Aziza, Hassen; Julien, Franck; Fornara, Pascal; Masson, Pascal; Ogier, Jean-Luc; Bert, Yannick |
| Source: |
IEEE Transactions on Electron Devices ; volume 60, issue 3, page 1263-1267 ; ISSN 0018-9383 1557-9646 |
| Publisher Information: |
Institute of Electrical and Electronics Engineers (IEEE) |
| Publication Year: |
2013 |
| Document Type: |
article in journal/newspaper |
| Language: |
unknown |
| DOI: |
10.1109/ted.2013.2237778 |
| Availability: |
https://doi.org/10.1109/ted.2013.2237778; http://xplorestaging.ieee.org/ielx5/16/6466448/06461399.pdf?arnumber=6461399 |
| Rights: |
https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html |
| Accession Number: |
edsbas.D62C233D |
| Database: |
BASE |