Hybrid Logic Style CMOS Full Adder Using 10-T XOR & XNOR Circuit
| Title: | Hybrid Logic Style CMOS Full Adder Using 10-T XOR & XNOR Circuit |
|---|---|
| Authors: | Suresh, N.; Gopal, Dhanalakshmi; Rosi, A.; Sivakumar, P.; Shahila, D. Ferlin Deva; A, Ashwini. |
| Source: | 2024 7th International Conference on Circuit Power and Computing Technologies (ICCPCT) ; page 245-249 |
| Publisher Information: | IEEE |
| Publication Year: | 2024 |
| Document Type: | conference object |
| Language: | unknown |
| DOI: | 10.1109/iccpct61902.2024.10672927 |
| Availability: | https://doi.org/10.1109/iccpct61902.2024.10672927; http://xplorestaging.ieee.org/ielx8/10672622/10672627/10672927.pdf?arnumber=10672927 |
| Rights: | https://doi.org/10.15223/policy-029 ; https://doi.org/10.15223/policy-037 |
| Accession Number: | edsbas.FFC6964B |
| Database: | BASE |