| Title: |
Meta's Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences |
| Authors: |
Coburn, Joel; Tang, Chunqiang; Asal, Sameer Abu; Agrawal, Neeraj; Chinta, Raviteja; Dixit, Harish; Dodds, Brian; Dwarakapuram, Saritha; Firoozshahian, Amin; Gao, Cao; Gondkar, Kaustubh; Graf, Tyler; Hu, Junhan; Huang, Jian; Hughes, Sterling; Hutchin, Adam; Jakka, Bhasker; Chen, Guoqiang Jerry; Kalyanaraman, Indu; Kamath, Ashwin; Kansal, Pankaj; Kazi, Erum; Levenstein, Roman; Maddury, Mahesh; Mastro, Alex; Medaiyese, Siji; Modi, Pritesh; Montgomery, Jack; Nadathur, Satish; Nagpal, Amit; Narasimha, Ashwin; Naumov, Maxim; Ozer, Eleanor; Park, Jongsoo; Ramani, Poorvaja; Reddy, Harikrishna; Reiss, David; Roy, Deboleena; Sekar, Sathish; Sharma, Arushi; Shetty, Pavan; Sukumaran-Rajam, Aravind; Tal, Eran; Tsai, Mike; Varshini, Shreya; Wareing, Richard; Wu, Olivia; Xie, Xiaolong; Yang, Jinghan; Yu, Hangchen; Zargar, Tanmay; Zeng, Zitong; Zhang, Feixiong; Matthews, Ajit; Jiao, Xun; Zhang, Jiyuan; Menage, Emmanuel; Stokke, Truls Edvard; Sourouri, Mohammed |
| Source: |
Proceedings of the 52nd Annual International Symposium on Computer Architecture. :1689-1702 |
| Availability: |
http://dl.acm.org/doi/10.1145/3695053.3731409 |
| Database: |
ACM Full-Text Collection |