| Title: |
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning |
| Authors: |
Mertens, H.; Hosseini, M.; Chiarella, T.; Zhou, D.; Wang, S.; Mannaert, G.; Dupuy, E.; Radisic, D.; Tao, Z.; Oniki, Y.; Hikavyy, A.; Rosseel, R.; Mingardi, A.; Choudhury, S.; Gowda, P. Puttarame; Sebaai, F.; Peter, A.; Vandersmissen, K.; Soulie, J.P.; Keersgieter, A. De; Lima, L. Petersen Barbosa; Cavalcante, C.; Batuk, D.; Martinez, G.T.; Geypen, J.; Seidel, F.; Paulussen, K.; Favia, P.; Boemmels, J.; Loo, R.; Wong, P.; Marquez, A. Sepulveda; Chan, B.T.; Mitard, J.; Subramanian, S.; Demuynck, S.; Litta, E. Dentoni; Horiguchi, N.; Samavedam, S.; Biesemans, S. |
| Source: |
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023 |
| Relation: |
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |