| Title: |
3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs |
| Authors: |
Mannaa, S.; Poittevin, A.; Marchand, C.; Deleruyelle, D.; Deveautour, B.; Bosio, A.; O'Connor, I.; Mukherjee, C.; Wang, Y.; Rezgui, H.; Deng, M.; Maneux, C.; Muller, J.; Pelloquin, S.; Moustakas, K.; Larrieu, G. |
| Source: |
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE J. Explor. Solid-State Comput. Devices Circuits Exploratory Solid-State Computational Devices and Circuits, IEEE Journal on. 9(2):116-123 Dec, 2023 |
| Database: |
IEEE Xplore Digital Library |