| Title: |
Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM |
| Authors: |
Ronga, D.; Xhafa, X.; Faehn, E.; Girard, P.; Vayssade, T.; Virazel, A. |
| Source: |
2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS) Design, Test and Technology of Integrated Systems (DTTIS), 2024 IEEE International Conference on. :1-6 Oct, 2024 |
| Relation: |
2024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS) |
| Database: |
IEEE Xplore Digital Library |