| Title: |
A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction |
| Authors: |
Mehta, Aakash Hasmukhray; Gaggatur, Javed S; Rashid, Mohammad M.; Dakshinamurthy, Sampath; Srinivasamurthy, Aruna Kumar Lakya; Goyal, Anil Kumar; Manam, Subbarao; Gupta, Harshit; Sukumar, Sandeep; Mishra, Vipin K; S, Koushik N; Nekkanti, Santosh; Mitra, Sambaran; Jadhav, Pooja K; ChandraShekar, Miryala; Humayun, Dudekula; Rifani, Michael C; Xie, Jianyong; Collins, Andrew P |
| Source: |
2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) VLSID VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2025 38th International Conference on. :487-492 Jan, 2025 |
| Relation: |
2025 38th International Conference on VLSI Design and 2025 24th International Conference on Embedded Systems (VLSID) |
| Database: |
IEEE Xplore Digital Library |