| Title: |
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating |
| Authors: |
Lin, Mu-Shan; Tsai, Chien-Chun; Li, Shenggao; Chen, Wei-Chih; Huang, Wen-Hung; Chen, Yu-Chi; Huang, Yu-Jie; Drake, Alan; Wen, Chin-Hua; Ranucci, Paul; Kuo, Hsin-Hung; Yin, Aidong; Yang, Shu-Chun; Mahmoudi, Farsheed; Ke, Han-Tzung; Li, Chao-Chieh; Cheng, Nai-Chen; Wang, Jimmy; Lin, Kevin; Liao, Harry; Huang, Jie-Ren; Wu, Meng-Hsuan; Hsieh, Kenny Cheng-Hsiang; Amatruda, Nicholas; Polanco, William; King, David; Basso, Todd; Kashem, Anwar |
| Source: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:586-588 Feb, 2025 |
| Relation: |
2025 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |