Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing
| Title: | Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing |
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| Authors: | Park, Y.; Jeong, J.; Noh, S.; Kim, D.; Kim, H.; Hun Kim, S.; Hyun Kang, D.; Ju Kim, M.; Cho, B.J. |
| Source: | IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 46(5):685-688 May, 2025 |
| Database: | IEEE Xplore Digital Library |