Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3-nm Technology Node
| Title: | Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3-nm Technology Node |
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| Authors: | Park, J.; Kim, H.; Jung, H.; Ra, C.; Jeon, J. |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 44(12):4691-4700 Dec, 2025 |
| Database: | IEEE Xplore Digital Library |