| Title: |
A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store |
| Authors: |
Miyake, J.; Maeda, T.; Nishimichi, Y.; Katsura, J.; Tainguchi, T.; Yamaguchi, S.; Edamatsu, H.; Watari, S.; Takagi, Y.; Tsuji, K.; Kuninobu, S.; Cox, S.; Duschatko, D.; MacGregor, D. |
| Source: |
1990 37th IEEE International Conference on Solid-State Circuits Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International. :42-43 1990 |
| Relation: |
1990 37th IEEE International Conference on Solid-State Circuits |
| Database: |
IEEE Xplore Digital Library |