veriSiM: Formal Verification of SPICE Netlists for MAGIC-Based Logic-in-Memory
| Title: | veriSiM: Formal Verification of SPICE Netlists for MAGIC-Based Logic-in-Memory |
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| Authors: | Jha, C.K.; Singh, S.; Qayyum, K.; Bende, A.; Hassan, M.; Rana, V.; Merchant, F.; Drechsler, R. |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 45(2):845-854 Feb, 2026 |
| Database: | IEEE Xplore Digital Library |