| Title: |
NanoStack Transistor Architecture for CMOS 7A Node and Beyond |
| Authors: |
Reboh, S.; Zhang, C.; Yamashita, T.; Li, W. K.; Xie, R.; Ando, T.; Bajpai, U.; Mazza, J.; Lanzillo, N.; Cho, E.; Zhou, H.; Strane, J.; Miller, E.; Satterlee, J.; Fan, S.; Sulehria, Y.; Sankarapandian, M.; Mochizuki, S.; Shanker, N.; Johnson, R.; Chu, A.; Khan, S.; Malley, M.; Tseng, W.-T.; Pujari, R.; Stuckert, E.; Tierney, L.; Li, J.; Belyansky, M.; Nasseri, M.; Putnam, N.; Hubbard, A.; Durrant, D.; Fulham, J.; Canaperi, D.; Skordas, S.; Seo, S.-C.; Gluschenkov, O.; Sherony, M.; Wang, J.; Zhu, Y.; Arnold, J.; Wynne, J.; Meli, L.; Peethala, B.; Zhang, J.; Tolbert, J.; Dechene, D.; Shahidi, G.; Edelstein, D.; Ramachandran, R.; Guo, D.; Narayanan, V.; Felix, N.; Standaert, T.; Jagannathan, H.; Sohn, D.-K.; Bu, H.; Khare, M. |
| Source: |
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2025 Symposium on. :1-3 Jun, 2025 |
| Relation: |
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |