| Title: |
Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor |
| Authors: |
Rassoul, N.; Labbate, L. A.; Eneman, G.; Fantini, A.; Ritzenthaler, R.; Prado, J. Loyo; Loo, R.; Devulder, W.; Dupuy, E.; Peissker, T.; Pacco, A.; Raut, H. K.; Eyben, P.; Canga, E.; Rosseel, E.; Sharma, A.; Oh, H.; Rawal, Y.; Beggiato, M.; Kim, J.; Jiang, Y.; Milenin, A. P.; Subhechha, S.; Mitard, J.; Crotti, D.; Lee, I.; Belmonte, A.; Kar, G. S. |
| Source: |
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2025 Symposium on. :1-3 Jun, 2025 |
| Relation: |
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |