| Title: |
A 16nm Fully Integrated SoC for Hardware-Aware Neural Architecture Search |
| Authors: |
Lin, Yu-Cheng; Huang, Ming-Shan; Wang, Jeng-Bang; Chen, Wen-Ching; Chang, Nian-Shyang; Lin, Chun-Pin; Chen, Chi-Shi; Chiueh, Tzi-Dar; Yang, Chia-Hsiang |
| Source: |
2025 IEEE European Solid-State Electronics Research Conference (ESSERC) Solid-State Electronics Research Conference (ESSERC), 2025 IEEE European. :397-400 Sep, 2025 |
| Relation: |
2025 IEEE European Solid-State Electronics Research Conference (ESSERC) |
| Database: |
IEEE Xplore Digital Library |