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A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode

Title:	A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
Authors:	Aoyagi, Y.; Nii, K.; Yabuuchi, M.; Tanaka, T.; Mizutani, K.; Hamada, M.; Ishii, Y.; Chi Chou, Y.; Cheng Liu, J.; Huang, C.; Peng, K.; Hsu, Y.; Wang, I.; Cheng, H.; Liao, H.; Jonathan Chang, T.
Source:	IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 61(4):1466-1476 Apr, 2026
Database:	IEEE Xplore Digital Library