| Title: |
Combined Trace Neural Network for Improved Design Extraction in Integrated Circuit Post-Silicon Verification and Validation Workflows |
| Authors: |
Haines, Emily; Pozderac, Preston; Balint, J. Timothy; Patel, Yash; Mattei, Ryan; Schaffranek, James; Waite, Adam R.; Juntiff, Tamara; Sale, Matt; Kimura, Adam |
| Source: |
2025 IEEE Physical Assurance and Inspection of Electronics (PAINE) Physical Assurance and Inspection of Electronics (PAINE), 2025 IEEE. :1-6 Oct, 2025 |
| Relation: |
2025 IEEE Physical Assurance and Inspection of Electronics (PAINE) |
| Database: |
IEEE Xplore Digital Library |