| Title: |
30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes |
| Authors: |
Wang, Xing; Du, Yucheng; Jiao, Tianhui; Wu, Defa; Chen, Xi; Tang, Miaoyu; Yang, Yi; Liu, Zhichao; Guo, An; Fu, Gaoming; Li, Peng; Dong, Jun; Liu, Bo; Liu, Xinning; Shan, Weiwei; Cai, Hao; Sun, Guangyu; Tong, Lin; Yang, Jun; Si, Xin |
| Source: |
2026 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2026 IEEE International. 69:512-514 Feb, 2026 |
| Relation: |
2026 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |