| Title: |
MADiC: A 3nm 7.4TOPS/mm2, 17.4TOPS/W Generative Diffusion Accelerator Enabled by Hardware-Compiler Co-Optimization of Memory Hierarchy and Operator Parallelism |
| Authors: |
Hsieh, Shih-Wei; Chen, Yi-Syuan; Tsai, Ping-Yuan; Lin, Ming-Hung; Cheng, Chia-Yuan; Hsu, Lien-Feng; Huang, Po-Hao; Chih, Hung-Wei; Chiang, Po-Han; Chang, Chia-Ming; Chiang, Ming-Hsuan; Yuan, Chia-Hung; Kuo, Sheng-Po; Uggu, Viswanath; Chan, Chun-Kun; Shih, Ming-En David; Tseng, Yu-Cheng; Cheng, Hsin-Ping; Huang, Stan; Chen, Chia-Ping; Chang, ShenKai; Wang, Chih-Ming; Yeh, Po-Yu; Liu, Jett; Chang, Yung-Chang; Ju, Chi-Cheng; Jou, Yucheun Kevin |
| Source: |
2026 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2026 IEEE International. 69:1-3 Feb, 2026 |
| Relation: |
2026 IEEE International Solid-State Circuits Conference (ISSCC) |
| Database: |
IEEE Xplore Digital Library |