| Title: |
Design and Analysis of 16-bit Vedic Multiplier using Peres Reversible Logic Gate |
| Authors: |
Jyothish, D; Nagaraj, S; Kumar, E Kishore; Kumar, G Hitesh; Rosireddy, A; Reddy, C Samhitha |
| Source: |
2025 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT) Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT), 2025 International Conference on. :1-6 Dec, 2025 |
| Relation: |
2025 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT) |
| Database: |
IEEE Xplore Digital Library |