RISC-V Area-Optimized ASIC Design with a Multi-Height 7nm FinFET Standard Cell Library
| Title: | RISC-V Area-Optimized ASIC Design with a Multi-Height 7nm FinFET Standard Cell Library |
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| Authors: | Lemos, Matheus; Farias, Clayton R.; Butzen, Paulo F.; Azambuja, Jose Rodrigo |
| Source: | 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS) Circuits and System (LASCAS), 2026 IEEE 17th Latin America Symposium on. :1-5 Feb, 2026 |
| Relation: | 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS) |
| Database: | IEEE Xplore Digital Library |