| Title: |
Modified and Optimized Architecture for 16-Bit Signed Magnitude Adder Using Carry Look-Ahead Adder on FPGA |
| Authors: |
Krishnan, Thiruvenkadam; Suresh Kumar, R.; Perry, Kenston; Godfrey, Philip; Pradyun, K. M. |
| Source: |
2026 4th International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA) Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA), 2026 4th International Conference on. :1-6 Apr, 2026 |
| Relation: |
2026 4th International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA) |
| Database: |
IEEE Xplore Digital Library |