| Title: |
Electrical Characteristics of the 4F2 Vertical Gate (VG) DRAM integrated with Bit Line Shielding (BLS) and Back Gate (BG) Transistor |
| Authors: |
Chu, Seung Wan; Cheon, Junho; Cho, Jinsun; Doh, Eunhyup; Han, Jungmin; Hong, Seung Bum; Kim, Choong-ki; Kim, Daeik; Kim, Jin Ar; Kim, Sunghyun; Kim, Yongtaik; Kum, Kyongsoo; Kwon, Sein; Lee, DongJae; Lee, Dong Ryeol; Lee, Junghak; Park, Eunshil; Park, Jongbum; Shin, Dong Hee; Shin, Eunji; Song, Jino; Sung, Minchul; Yoo, Wansik; Hwang, JeongTae; Kim, Seungbum; Jang, Kyoungchul; Park, Joodong; Cho, Youngmann; Cha, Seonyong |
| Source: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2026 IEEE/JSAP Symposium on. :1-3 Jun, 2026 |
| Relation: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |