| Title: |
First EUV-Enabled Integration Route for 50 nm Pitch N and PMOS Transistors with 2D Materials Channel from a 300 mm Fab |
| Authors: |
Schram, T.; Smets, Q.; Arutchelvan, G.; Yao, C.-H.; Chou, S.A.; Li, M.-Y.; Batuk, D.; Rodrigues, T.; Ghosh, S.; Kumar, P.; Groven, B.; Opdebeeck, A.; Alvarez, D.M.; Jiang, Y.; Sarkar, T.; Kellens, K.; Vrancken, E.; Da Silva, C. R.; Mogultay, C.; Shen, T-H; Faramarzi, V.; Kar, G. S.; de la Rosa, C. J. Lockhart; van Dal, M.; Yen, A.; Radu, I. P.; De Poortere, E. |
| Source: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2026 IEEE/JSAP Symposium on. :1-3 Jun, 2026 |
| Relation: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |