| Title: |
Area and Performance of Staggered-Channel Nanostack SRAM Bitcells |
| Authors: |
Zhang, Chen; Radens, Carl; Bajpai, Utkarsh; Reboh, Shay; Khan, Shahrukh; Deming, Matt; Jain, Nikhil; Lanzillo, Nick; Seshadri, Indira; Sarkar, Debarghya; Mignot, Yann; Shanker, Nirmaan; Sieg, Stuart; Younus, Imran; Akter, Shirin; Liu, Feng; Rana, Uzma; Fan, Susan; Ramachandran, Ravi; Yamashita, Tenko; Guo, Dechao; Bu, Huiming |
| Source: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2026 IEEE/JSAP Symposium on. :1-3 Jun, 2026 |
| Relation: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |