| Title: |
Dual-Phase Offset Compensation and Conditional Latch Gating for a Fully Singleended Dram Core Data-Line Architecture Operating at 0.75 V |
| Authors: |
Lee, Chang-Young; Park, Young-Seok; Park, Hyeon-Jin; Shin, Dong-Hak; Park, Keon-Woo; Yoon, Se-Ryeong; Lee, Dong-Kyu; Kim, Min-Soo; Sung, Gi-Jong; Kang, Kyu-Chang; Kim, Sang-Yun; Yoon, Hyun-Chul; Won, Bok-Yeon; Nam, In-Cheol; Seo, Young-Hun; Bae, Seung-Jun; Sohn, Young-Soo; Hwang, Sang-Jun |
| Source: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2026 IEEE/JSAP Symposium on. :1-3 Jun, 2026 |
| Relation: |
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Database: |
IEEE Xplore Digital Library |