Wire length distribution model considering core utilization for system on chip
| Title: | Wire length distribution model considering core utilization for system on chip |
|---|---|
| Authors: | Kyogoku, T.; Inoue, J.; Nakashima, H.; Uezono, T.; Okada, K.; Masu, K. |
| Source: | IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) VLSI VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. :276-277 2005 |
| Relation: | Proceedings. IEEE Computer Society Annual Symposium on VLSI |
| Database: | IEEE Xplore Digital Library |