1.5 mu m CMOS gate arrays with analog/digital macros designed using common base arrays
| Title: | 1.5 mu m CMOS gate arrays with analog/digital macros designed using common base arrays |
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| Authors: | Kawada, S.; Hara, Y.; Isono, T.; Inuzuka, T. |
| Source: | IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 24(4):985-990 Aug, 1989 |
| Database: | IEEE Xplore Digital Library |