| Title: |
High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout |
| Authors: |
Horiguchi, N.; Demuynck, S.; Ercken, M.; Locorotondo, S.; Lazzarino, F.; Altamirano, E.; Huffman, C.; Brus, S.; Demand, M.; Struyf, H.; De Backer, J.; Hermans, J.; Delvaux, C.; Vandeweyer, T.; Baerts, C.; Mannaert, G.; Truffert, V.; Verluijs, J.; Alaerts, W.; Dekkers, H.; Ong, P.; Heylen, N.; Kellens, K.; Volders, H.; Hikavyy, A.; Vrancken, C.; Rakowski, M.; Verhaegen, S.; Vandenberghe, G.; Beyer, G.; Lauwers, A.; Absil, P.; Hoffman, T.; Ronse, K.; Biesemans, S. |
| Source: |
2010 Symposium on VLSI Technology VLSI Technology (VLSIT), 2010 Symposium on. :23-24 Jun, 2010 |
| Relation: |
2010 IEEE Symposium on VLSI Technology |
| Database: |
IEEE Xplore Digital Library |