From design-time concurrency to effective implementation parallelism: The multi-clock reactive case
| Title: | From design-time concurrency to effective implementation parallelism: The multi-clock reactive case |
|---|---|
| Authors: | Papailiopoulou, V.; Potop-Butucaru, D.; Sorel, Y.; de Simone, R.; Besnard, L.; Talpin, J.-P. |
| Source: | 2011 Electronic System Level Synthesis Conference (ESLsyn) Electronic System Level Synthesis Conference (ESLsyn), 2011. :1-6 Jun, 2011 |
| Relation: | 2011 Electronic System Level Synthesis Conference (ESLsyn) |
| Database: | IEEE Xplore Digital Library |