Design enablement for yield and area optimization at 20 nm and below
| Title: | Design enablement for yield and area optimization at 20 nm and below |
|---|---|
| Authors: | Brotman, Andrew; Capodieci, Luigi; Liu, Bill; Rashed, Mahbub; Kye, Jongwook; Kengeri, Subramani; Venkatesan, Suresh |
| Source: | 2011 Symposium on VLSI Technology - Digest of Technical Papers VLSI Technology (VLSIT), 2011 Symposium on. :108-109 Jun, 2011 |
| Relation: | 2011 IEEE Symposium on VLSI Technology |
| Database: | IEEE Xplore Digital Library |