32-bit reconfigurable logic-BIST design using Verilog for ASIC chips
| Title: | 32-bit reconfigurable logic-BIST design using Verilog for ASIC chips |
|---|---|
| Authors: | Bhakthavatchalu, Ramesh; Deepthy, G R; Sreenivasa Mallia, S; HariKrishnan, R; Krishnan, Arun; Sruthi, B. |
| Source: | 2011 IEEE Recent Advances in Intelligent Computational Systems Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE. :386-390 Sep, 2011 |
| Relation: | 2011 IEEE Recent Advances in Intelligent Computational Systems (RAICS) |
| Database: | IEEE Xplore Digital Library |