DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
| Title: | DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks |
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| Authors: | Deutsch, Sergej; Keller, Brion; Chickermane, Vivek; Mukherjee, Subhasish; Sood, Navdeep; Goel, Sandeep Kumar; Chen, Ji-Jan; Mehta, Ashok; Lee, Frank; Marinissen, Erik Jan |
| Source: | 2012 IEEE International Test Conference Test Conference (ITC), 2012 IEEE International. :1-10 Nov, 2012 |
| Relation: | 2012 IEEE International Test Conference (ITC) |
| Database: | IEEE Xplore Digital Library |