100Gb/s ethernet chipsets in 65nm CMOS technology
| Title: | 100Gb/s ethernet chipsets in 65nm CMOS technology |
|---|---|
| Authors: | Jiang, Jhih-Yu; Chiang, Ping-Chuan; Hung, Hao-Wei; Lin, Chen-Lun; Yoon, Ty; Lee, Jri |
| Source: | 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. :120-121 Feb, 2013 |
| Relation: | 2013 IEEE International Solid-State Circuits Conference - (ISSCC) |
| Database: | IEEE Xplore Digital Library |