A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
| Title: | A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process |
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| Authors: | Doi, Y.; Shibasaki, T.; Danjo, T.; Chaivipas, W.; Hashida, T.; Miyaoka, H.; Hoshino, M.; Koyanagi, Y.; Yamamoto, T.; Tsukamoto, S.; Tamura, H. |
| Source: | IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 48(12):3258-3267 Dec, 2013 |
| Database: | IEEE Xplore Digital Library |