Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling
| Title: | Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling |
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| Authors: | Zhang, Shanghang; Li, Xin; Blanton, R. D.; da Silva, Jose Machado; Carulli, John M.; Butler, Kenneth M. |
| Source: | 2014 International Test Conference Test Conference (ITC), 2014 IEEE International. :1-10 Oct, 2014 |
| Relation: | 2014 IEEE International Test Conference (ITC) |
| Database: | IEEE Xplore Digital Library |