Design Methodology for Voltage-Scaled Clock Distribution Networks
| Title: | Design Methodology for Voltage-Scaled Clock Distribution Networks |
|---|---|
| Authors: | Sitik, C.; Liu, W.; Taskin, B.; Salman, E. |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 24(10):3080-3093 Oct, 2016 |
| Database: | IEEE Xplore Digital Library |