A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
| Title: | A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors |
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| Authors: | Torrens, G.; Alorda, B.; Carmona, C.; Malagon-Perianez, D.; Segura, J.; Bota, S. |
| Source: | IEEE Transactions on Emerging Topics in Computing IEEE Trans. Emerg. Topics Comput. Emerging Topics in Computing, IEEE Transactions on. 7(3):447-455 Sep, 2019 |
| Database: | IEEE Xplore Digital Library |