| Title: |
Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization |
| Authors: |
Ritzenthaler, R.; Mertens, H.; Pena, V.; Santoro, G.; Chasin, A.; Kenis, K.; Devriendt, K.; Mannaert, G.; Dekkers, H.; Dangol, A.; Lin, Y.; Sun, S.; Chen, Z.; Kim, M.; Machillot, J.; Mitard, J.; Yoshida, N.; Kim, N.; Mocuta, D.; Horiguchi, N. |
| Source: |
2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :21.5.1-21.5.4 Dec, 2018 |
| Relation: |
2018 IEEE International Electron Devices Meeting (IEDM) |
| Database: |
IEEE Xplore Digital Library |